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JSS
2006
104views more  JSS 2006»
13 years 4 months ago
Modelling and simulation of off-chip communication architectures for high-speed packet processors
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
Jacob Engel, Daniel Lacks, Taskin Koçak
DAC
2002
ACM
14 years 5 months ago
A framework for evaluating design tradeoffs in packet processing architectures
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
Lothar Thiele, Matthias Gries, Samarjit Chakrabort...
ANCS
2006
ACM
13 years 8 months ago
Efficient memory utilization on network processors for deep packet inspection
Deep Packet Inspection (DPI) refers to examining both packet header and payload to look for predefined patterns, which is essential for network security, intrusion detection and c...
Piti Piyachon, Yan Luo
SIGCOMM
2009
ACM
13 years 11 months ago
PLUG: flexible lookup modules for rapid deployment of new protocols in high-speed routers
New protocols for the data link and network layer are being proposed to address limitations of current protocols in terms of scalability, security, and manageability. High-speed r...
Lorenzo De Carli, Yi Pan, Amit Kumar, Cristian Est...
GLOBECOM
2007
IEEE
13 years 10 months ago
AMBER Sched: An Analytical Model Based Resource Scheduler for Programmable Routers
—The growth of the Internet in the last years has been pushed by increasing requirements in terms of capacity, security and reliability. Moreover, improvements in multimedia appl...
Domenico Ficara, Stefano Giordano, Michele Pagano,...