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MICRO
2003
IEEE
258views Hardware» more  MICRO 2003»
13 years 9 months ago
LLVA: A Low-level Virtual Instruction Set Architecture
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
Vikram S. Adve, Chris Lattner, Michael Brukman, An...
IPPS
2010
IEEE
13 years 2 months ago
A GPU-inspired soft processor for high-throughput acceleration
There is building interest in using FPGAs as accelerators for high-performance computing, but existing systems for programming them are so far inadequate. In this paper we propose...
Jeffrey Kingyens, J. Gregory Steffan
ACSD
2006
IEEE
148views Hardware» more  ACSD 2006»
13 years 10 months ago
Functional Model Exploration for Multimedia Applications via Algebraic Operators
An optimized functional design space exploration method for multimedia applications is proposed. The basis of the method is a way of representing the dependency and the concurrenc...
Shinjiro Kakita, Yosinori Watanabe, Douglas Densmo...
POS
1994
Springer
13 years 8 months ago
Concurrent Shadow Paging in the Flask Architecture
The differing requirements for concurrency models in programming languages and databases are widely diverse and often seemingly incompatible. The rigid provision of a particular c...
David S. Munro, Richard C. H. Connor, Ronald Morri...
WSCG
2001
108views more  WSCG 2001»
13 years 5 months ago
Co-Operative and Concurrent Blending Motion Generators
In this paper we will be describing a new animation architecture and its implementation in our system LIVE. This model introduces a new blending layer approach which uses several ...
Vincent Bonnafous, Eric Menou, Jean-Pierre Jessel,...