3 search results - page 1 / 1 » Modulo Scheduling with Cache Reuse Information |
EUROPAR
1997
Springer
13 years 8 months ago
1997
Springer
Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contrib...
IPPS
2006
IEEE
13 years 10 months ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Utilizing on-chip caches in embedded multiprocessorsystem-on-a-chip (MPSoC) based systems is critical from both performance and power perspectives. While most of the prior work th...