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» Multi-Domain Clock Skew Scheduling
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ICCAD
1999
IEEE
153views Hardware» more  ICCAD 1999»
13 years 9 months ago
Cycle time and slack optimization for VLSI-chips
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
Christoph Albrecht, Bernhard Korte, Jürgen Sc...
LATIN
2004
Springer
13 years 10 months ago
Global Synchronization in Sensornets
Time synchronization is necessary in many distributed systems, but achieving synchronization in sensornets, which combine stringent precision requirements with severe resource con...
Jeremy Elson, Richard M. Karp, Christos H. Papadim...
SIPS
2006
IEEE
13 years 11 months ago
Low Power Trellis Decoder with Overscaled Supply Voltage
Abstract— This paper is interested in applying voltage overscaling (VOS) to reduce trellis decoder energy consumption, where the key issue is how to minimize the decoding perform...
Yang Liu, Tong Zhang, Jiang Hu
ISLPED
2004
ACM
124views Hardware» more  ISLPED 2004»
13 years 10 months ago
Application adaptive energy efficient clustered architectures
As clock frequency and die area increase, achieving energy efficiency, while distributing a low skew, global clock signal becomes increasingly difficult. Challenges imposed by dee...
Diana Marculescu
DAC
2003
ACM
14 years 6 months ago
Pushing ASIC performance in a power envelope
Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best pow...
Ruchir Puri, Leon Stok, John M. Cohn, David S. Kun...