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» Multi-Valued Logic Synthesis
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VLSID
1999
IEEE
86views VLSI» more  VLSID 1999»
13 years 8 months ago
Multi-Valued Logic Synthesis
We survey some of the methods used for manipulating, representing, and optimizing multi-valued logic with the view of both building a better understanding of the more specialized ...
Robert K. Brayton, Sunil P. Khatri
ICCAD
2000
IEEE
113views Hardware» more  ICCAD 2000»
13 years 8 months ago
Don't Cares and Multi-Valued Logic Network Minimization
We address optimizing multi-valued (MV) logic functions in a multi-level combinational logic network. Each node in the network, called an MV-node, has multi-valued inputs and sing...
Yunjian Jiang, Robert K. Brayton
ISMVL
2007
IEEE
102views Hardware» more  ISMVL 2007»
13 years 10 months ago
A Generalization of the Deutsch-Jozsa Algorithm to Multi-Valued Quantum Logic
We generalize the binary Deutsch-Jozsa algorithm to nvalued logic using the quantum Fourier transform. Our algorithm is not only able to distinguish between constant and balanced ...
Yale Fan
MEMOCODE
2007
IEEE
13 years 10 months ago
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
Stephan Eggersglüß, Görschwin Fey,...
ISMVL
2003
IEEE
101views Hardware» more  ISMVL 2003»
13 years 9 months ago
Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic
Ki-Whan Song, Sang-Hoon Lee, Dae Hwan Kim, Kyung R...