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ISSS
2002
IEEE
133views Hardware» more  ISSS 2002»
13 years 9 months ago
Efficient Simulation of Synthesis-Oriented System Level Designs
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware system...
Rajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu
ASPDAC
2011
ACM
183views Hardware» more  ASPDAC 2011»
12 years 8 months ago
Multi-core parallel simulation of System-level Description Languages
Rainer Dömer, Weiwei Chen, Xu Han, Andreas Ge...
FDL
2003
IEEE
13 years 9 months ago
Design and Power Analysis in SysteC of an I2C Bus Driver
The paper presents a methodology to integrate information on power consumption in a high level functional description of a System-on-chip. The power dissipated during the executio...
Marco Caldari, Massimo Conti, Paolo Crippa, Simone...
EUROMICRO
1999
IEEE
13 years 8 months ago
Software Synthesis for System Level Design Using Process Execution Trees
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
Leo J. van Bokhoven, Jeroen Voeten, Marc Geilen
IPPS
2003
IEEE
13 years 9 months ago
The CoGenT Project: Co-Generating Compilers and Simulators for Dynamically Compiled Languages
To understand the performance of modern Java systems one must observe execution in the context of specific architectures. It is also important that we make these observations usi...
J. Eliot B. Moss, Charles C. Weems, Timothy Richar...