9 search results - page 1 / 2 » Multi-frequency wrapper design and optimization for embedded... |
DAC
2005
ACM
13 years 6 months ago
2005
ACM
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
Abstract-- This paper proposes a novel power-aware multifrequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time a...
MTDT
2003
IEEE
13 years 9 months ago
2003
IEEE
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract— Power consumption has become a crucial problem in modern circuit design. Multiple Supply Voltage (MSV) design is introduced to provide higher flexibility in controllin...
ISLPED
2000
ACM
13 years 9 months ago
2000
ACM
Memory-processor integration o ers new opportunities for reducing the energy of a system. In the case of embedded systems, one solution consists of mapping the most frequently acc...