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» Multi-level clustering for clock skew optimization
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ICCAD
2009
IEEE
123views Hardware» more  ICCAD 2009»
9 years 3 months ago
Multi-level clustering for clock skew optimization
Clock skew scheduling has been effectively used to reduce the clock period of sequential circuits. However, this technique may become impractical if a different skew must be appli...
Jonas Casanova, Jordi Cortadella
ISPD
2007
ACM
99views Hardware» more  ISPD 2007»
9 years 7 months ago
Minimal skew clock embedding considering time variant temperature gradient
The existing temperature-aware clock embedding assumes a time-invariant temperature gradient. However, it is not solved how to find the worst-case temperature gradient leading to...
Hao Yu, Yu Hu, Chunchen Liu, Lei He
ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
10 years 23 days ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
9 years 10 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
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