2 search results - page 1 / 1 » Multiple-Valued Minimization to Optimize PLAs with Output EX... |
ISMVL
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper considers an optimization method of programmable logic arrays (PLAs), which have two-input EXOR gate at the outputs. The PLA realizes an EXOR of two sum-of-products exp...
ISMVL
1994
IEEE
13 years 9 months ago
1994
IEEE
The paper proposes mvTANTs, three-level networks with multiple-valued inputs and binary outputs. These networks are a generalization of binary TANTs (Three level And Not networks...