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CDES
2006
158views Hardware» more  CDES 2006»
13 years 7 months ago
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia
DSD
2003
IEEE
97views Hardware» more  DSD 2003»
13 years 11 months ago
A Quadruple Precision and Dual Double Precision Floating-Point Multiplier
Double precision floating-point arithmetic is inadequate for many scientific computations. This paper presents the design of a quadruple precision floating-point multiplier tha...
Ahmet Akkas, Michael J. Schulte
SIGARCH
2010
69views more  SIGARCH 2010»
13 years 15 days ago
Multipliers for floating-point double precision and beyond on FPGAs
Sebastian Banescu, Florent de Dinechin, Bogdan Pas...
ERSA
2004
130views Hardware» more  ERSA 2004»
13 years 7 months ago
Computing Lennard-Jones Potentials and Forces with Reconfigurable Hardware
Abstract-- Technological advances have made FPGAs an attractive platform for the acceleration of complex scientific applications. These applications demand high performance and hig...
Ronald Scrofano, Viktor K. Prasanna
DAGSTUHL
2008
13 years 7 months ago
A Modified Staggered Correction Arithmetic with Enhanced Accuracy and Very Wide Exponent Range
Abstract. A so called staggered precision arithmetic is a special kind of a multiple precision arithmetic based on the underlying floating point data format (typically IEEE double ...
Frithjof Blomquist, Werner Hofschuster, Walter Kr&...