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SAMOS
2004
Springer
13 years 10 months ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope
UM
2001
Springer
13 years 9 months ago
Recognizing Time Pressure and Cognitive Load on the Basis of Speech: An Experimental Study
In an experimental environment, we simulated the situation of a user who gives speech input to a system while walking through an airport. The time pressure on the subjects and the ...
Christian A. Müller, Barbara Großmann-H...
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
13 years 10 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni