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ICDCS
2005
IEEE
13 years 10 months ago
Network-Centric Buffer Cache Organization
A pass-through server such as an NFS server backed by an iSCSI[1] storage server only passes data between the storage server and NFS clients. Ideally it should require at most one...
Gang Peng, Srikant Sharma, Tzi-cker Chiueh
ISCA
1997
IEEE
103views Hardware» more  ISCA 1997»
13 years 8 months ago
Designing High Bandwidth On-Chip Caches
In this paper we evaluate the performance of high bandwidth caches that employ multiple ports, multiple cycle hit times, on-chip DRAM, and a line buffer to find the organization t...
Kenneth M. Wilson, Kunle Olukotun
DATE
2009
IEEE
118views Hardware» more  DATE 2009»
13 years 11 months ago
Limiting the number of dirty cache lines
Abstract—Caches often employ write-back instead of writethrough, since write-back avoids unnecessary transfers for multiple writes to the same block. For several reasons, however...
Pepijn J. de Langen, Ben H. H. Juurlink
ISLPED
2010
ACM
128views Hardware» more  ISLPED 2010»
13 years 2 months ago
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips redu...
Ahmed M. Amin, Zeshan Chishti
ICDE
2005
IEEE
158views Database» more  ICDE 2005»
14 years 5 months ago
Cache-Conscious Automata for XML Filtering
Hardware cache behavior is an important factor in the performance of memory-resident, data-intensive systems such as XML filtering engines. A key data structure in several recent ...
Bingsheng He, Qiong Luo, Byron Choi