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» Neural Compiler Technology for a Parallel Architecture
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IPPS
1999
IEEE
13 years 10 months ago
DEFACTO: A Design Environment for Adaptive Computing Technology
The lack of high-level design tools hampers the widespread adoption of adaptive computing systems. Application developers have to master a wide range of functions, from the high-le...
Kiran Bondalapati, Pedro C. Diniz, Phillip Duncan,...
CDES
2006
184views Hardware» more  CDES 2006»
13 years 7 months ago
Compilation for Future Nanocomputer Architectures
Compilation has a long history of translating a programmer's human-readable code into machine instructions designed to make good use of a specific target computer. In this pa...
Thomas P. Way
ISCAPDCS
2007
13 years 7 months ago
Architectural requirements of parallel computational biology applications with explicit instruction level parallelism
—The tremendous growth in the information culture, efficient digital searches are needed to extract and identify information from huge data. The notion that evolution in silicon ...
Naeem Zafar Azeemi
IEEEPACT
2002
IEEE
13 years 10 months ago
Using the Compiler to Improve Cache Replacement Decisions
Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with L...
Zhenlin Wang, Kathryn S. McKinley, Arnold L. Rosen...
HCW
1999
IEEE
13 years 10 months ago
An On-Line Performance Visualization Technology
We present a new software technology for on-line performance analysis and visualization of complex parallel and distributed systems. Often heterogeneous, these systems need capabi...
Aleksandar M. Bakic, Matt W. Mutka, Diane T. Rover