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DATE
2005
IEEE
235views Hardware» more  DATE 2005»
13 years 10 months ago
Challenges in Embedded Memory Design and Test
Both the number of embedded memories, as well as the total embedded memory content in our chips is growing steadily. Time for chip designers, EDA makers, and test engineers to upd...
Erik Jan Marinissen, Betty Prince, Doris Keitel-Sc...
HIPC
2000
Springer
13 years 8 months ago
Instruction Level Distributed Processing
Within two or three technology generations, processor architects will face a number of major challenges. Wire delays will become critical, and power considerations will temper the ...
James E. Smith
MICRO
2003
IEEE
152views Hardware» more  MICRO 2003»
13 years 10 months ago
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...
Shubhendu S. Mukherjee, Christopher T. Weaver, Joe...
ISCA
2006
IEEE
145views Hardware» more  ISCA 2006»
13 years 4 months ago
Techniques for Multicore Thermal Management: Classification and New Exploration
Power density continues to increase exponentially with each new technology generation, posing a major challenge for thermal management in modern processors. Much past work has exa...
James Donald, Margaret Martonosi