17 search results - page 4 / 4 » Next Cache Line and Set Prediction |
HPCA
2004
IEEE
14 years 5 months ago
2004
IEEE
This paper proposes and evaluates hardware mechanisms for supporting prescient instruction prefetch--an approach to improving single-threaded application performance by using help...
ASPLOS
2009
ACM
14 years 5 months ago
2009
ACM
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and pe...