18 search results - page 3 / 4 » Non-fractional parallelism in LDPC decoder implementations |
FCCM
2008
IEEE
14 years 7 days ago
2008
IEEE
We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding. This architecture template has been instantiated in the case of the...
DSD
2008
IEEE
14 years 7 days ago
2008
IEEE
We propose a parallel and modular architecture well suited to 802.16e WiMax LDPC code decoding. The proposed design is fully compliant with all the code classes defined by the Wi...
VTC
2008
IEEE
14 years 4 days ago
2008
IEEE
—Turbo DeCodulation is the combination of iterative demodulation and iterative source-channel decoding in a multiple Turbo process. The receiver structures of bit-interleaved cod...
ICASSP
2011
IEEE
12 years 9 months ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
ASPDAC
2004
ACM
13 years 11 months ago
2004
ACM
Channel coding is an important building block in communication systems since it ensures the quality of service. Irregular repeat-accumulate (IRA) codes belong to the class of Low-...