26 search results - page 2 / 6 » Non-local Instruction Scheduling with Limited Code Growth |
ICS
1999
Tsinghua U.
13 years 9 months ago
1999
Tsinghua U.
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
MICRO
2007
IEEE
13 years 11 months ago
2007
IEEE
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
Abstract-- The design of application-specific instruction set processor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design...
MICRO
1993
IEEE
13 years 9 months ago
1993
IEEE
Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents some results of our investigation into ways to modify MIM...
ISSS
1999
IEEE
13 years 9 months ago
1999
IEEE
Code generation methods for digital signal processors are increasingly hampered by the combination of tight timing constraints imposed by the algorithms and the limited capacity o...