Sciweavers

11 search results - page 1 / 3
» Non-tree routing for reliability and yield improvement
Sort
View
ICCAD
2002
IEEE
161views Hardware» more  ICCAD 2002»
14 years 1 months ago
Non-tree routing for reliability and yield improvement
We propose to introduce redundant interconnects for manufacturing yield and reliability improvement. By introducing redundant interconnects, the potential for open faults is reduc...
Andrew B. Kahng, Bao Liu, Ion I. Mandoiu
ICCAD
2009
IEEE
92views Hardware» more  ICCAD 2009»
13 years 2 months ago
How to consider shorts and guarantee yield rate improvement for redundant wire insertion
This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip yield rate improvement for redundant wire insertion. Without considering yield ra...
Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak
GLVLSI
2009
IEEE
125views VLSI» more  GLVLSI 2009»
13 years 11 months ago
Redundant wire insertion for yield improvement
Based on the insertion of internal and external redundant wires into L-type and U-type wires, an efficient two-phase reliability-driven insertion algorithm is proposed to insert r...
Jin-Tai Yan, Zhi-Wei Chen
ICCCN
2007
IEEE
13 years 10 months ago
On Improving the Reliability of Packet Delivery in Dense Wireless Sensor Networks
—Wireless sensor networks (WSN) built using current Berkeley Mica motes exhibit low reliability for packet delivery. There is anecdotal evidence of poor packet delivery rates fro...
JunSuk Shin, Umakishore Ramachandran, Mostafa H. A...
TCAD
2008
119views more  TCAD 2008»
13 years 4 months ago
Full-Chip Routing Considering Double-Via Insertion
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, ...
Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lum...