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EUROPAR
2005
Springer
13 years 9 months ago
Non-uniform Instruction Scheduling
Dynamic instruction scheduling logic is one of the most critical and cycle-limiting structures in modern superscalar processors, and it is not easily pipelined without significant ...
Joseph J. Sharkey, Dmitry V. Ponomarev
JISE
2002
65views more  JISE 2002»
13 years 3 months ago
A Release Combined Scheduling Scheme for Non-Uniform Dependence Loops
Der-Lin Pean, Huey-Ting Chua, Cheng Chen
SPDP
1991
IEEE
13 years 7 months ago
Local vs. global memory in the IBM RP3: experiments and performance modelling
A number of experiments regarding the placement of instructions, private data and shared data in the Non-Uniform-Memory-Access multiprocessor, RP3 has been performed. Three Scient...
Mats Brorsson
ISPASS
2010
IEEE
13 years 11 months ago
Memphis: Finding and fixing NUMA-related performance problems on multi-core platforms
—Until recently, most high-end scientific applications have been immune to performance problems caused by NonUniform Memory Access (NUMA). However, current trends in micro-proces...
Collin McCurdy, Jeffrey S. Vetter
PVM
2010
Springer
13 years 2 months ago
Adaptive MPI Multirail Tuning for Non-uniform Input/Output Access
Multicore processors have not only reintroduced Non-Uniform Memory Access (NUMA) architectures in nowadays parallel computers, but they are also responsible for non-uniform access ...
Stephanie Moreaud, Brice Goglin, Raymond Namyst