33 search results - page 6 / 7 » Nonlinear array layouts for hierarchical memory systems |
ICCD
2005
IEEE
14 years 2 months ago
2005
IEEE
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
ESA
1998
Springer
13 years 9 months ago
1998
Springer
Abstract. Data sets in large applications are often too massive to t completely inside the computer's internal memory. The resulting input output communication or I O between ...
SCOPES
2004
Springer
13 years 10 months ago
2004
Springer
For mobile embedded systems, the energy consumption is a limiting factor because of today’s battery capacities. Besides the processor, memory accesses consume a high amount of en...
ISCA
2010
IEEE
13 years 10 months ago
2010
IEEE
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
TPDS
2010
13 years 3 months ago
2010
—This paper presents the development and implementation of a multiprocessor system-on-chip solution for fast and real time simulations of complex and nonlinear wheel-rail contact...