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» Novel Pin Assignment Algorithms for Components with Very Hig...
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DATE
2008
IEEE
103views Hardware» more  DATE 2008»
13 years 11 months ago
Novel Pin Assignment Algorithms for Components with Very High Pin Counts
The wiring effort and thus, the routability of electronic designs such as printed circuit boards, multi chip modules and single chip modules largely depends on the assignment of s...
Tilo Meister, Jens Lienig, Gisbert Thomke
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
13 years 8 months ago
Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling
This paper proposes Noise-Direct, a design methodology for power integrity aware floorplanning, using microarchitectural feedback to guide module placement. Stringent power constr...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
ISCAS
2003
IEEE
131views Hardware» more  ISCAS 2003»
13 years 9 months ago
Process variation dimension reduction based on SVD
We propose an algorithm based on singular value decomposition (SVD) to reduce the number of process variation variables. With few process variation variables, fault simulation and...
Zhuo Li, Xiang Lu, Weiping Shi
PPOPP
2010
ACM
14 years 1 months ago
Scaling LAPACK panel operations using parallel cache assignment
In LAPACK many matrix operations are cast as block algorithms which iteratively process a panel using an unblocked algorithm and then update a remainder matrix using the high perf...
Anthony M. Castaldo, R. Clint Whaley
SIGIR
2003
ACM
13 years 9 months ago
HAT: a hardware assisted TOP-DOC inverted index component
A novel Hardware Assisted Top-Doc (HAT) component is disclosed. HAT is an optimized content indexing device based on a modified inverted index structure. HAT accommodates patterns...
S. Kagan Agun, Ophir Frieder