24 search results - page 2 / 5 » Novel architectures for efficient (m, n) parallel counters |
LCPC
2004
Springer
13 years 11 months ago
2004
Springer
Trimaran is an integrated compilation and performance monitoring infrastructure. The architecture space that Trimaran covers is characterized by HPL-PD, a parameterized processor a...
IPPS
1999
IEEE
13 years 10 months ago
1999
IEEE
Clustering and scheduling of tasks for parallel implementation is a well researched problem. Several techniques have been presented in the literature to improve performance and re...
JCM
2008
13 years 5 months ago
2008
Optical Code Division Multiple Access (OCDMA) is considered as the strongest candidates for the future high speed optical networks due to the large bandwidth offered by the system,...
IPPS
2005
IEEE
13 years 11 months ago
2005
IEEE
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
ISHPC
1999
Springer
13 years 10 months ago
1999
Springer
Superscalar microprocessor efficiency is generally not as high as anticipated. In fact, sustained utilization below thirty percent of peak is not uncommon, even for fully optimized...