14 search results - page 1 / 3 » Off-Line Testing of Delay Faults in NoC Interconnects |
DSD
2006
IEEE
13 years 10 months ago
2006
IEEE
Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when th...
ETS
2007
IEEE
13 years 10 months ago
2007
IEEE
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address dri...
ISQED
2007
IEEE
13 years 10 months ago
2007
IEEE
Abstract—A Network-on-Chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected...
DATE
2007
IEEE
13 years 10 months ago
2007
IEEE
1 This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the ...
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
The interconnection network consumes the majority of die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple inter...