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» On Applying Incremental Satisfiability to Delay Fault Testin...
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ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
8 years 9 months ago
Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes
- Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift t...
Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz
JISE
2000
68views more  JISE 2000»
8 years 5 months ago
Testable Path Delay Fault Cover for Sequential Circuits
We present an algorithm for identifyinga set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently aect th...
Angela Krstic, Srimat T. Chakradhar, Kwang-Ting Ch...
ITC
2003
IEEE
120views Hardware» more  ITC 2003»
8 years 10 months ago
High Quality ATPG for Delay Defects
: The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture smalldistributed delay de...
Puneet Gupta, Michael S. Hsiao
VTS
2007
IEEE
71views Hardware» more  VTS 2007»
8 years 11 months ago
Optimizing Test Length for Soft Faults in DRAM Devices
: Soft faults in DRAMs are faults that do not get sensitized directly after an operation is performed, but require a time to pass before the fault can be detected. Tests developed ...
Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev
ASPDAC
2004
ACM
112views Hardware» more  ASPDAC 2004»
8 years 10 months ago
Longest path selection for delay test under process variation
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, We...
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