43 search results - page 6 / 9 » On Applying Incremental Satisfiability to Delay Fault Testin... |
DAC
2003
ACM
14 years 6 months ago
2003
ACM
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal tra...
DAC
1994
ACM
13 years 9 months ago
1994
ACM
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...
CEE
2006
13 years 5 months ago
2006
The need for reliable data communication performed in critical conditions and the respect of real-time constraints is an open issue in radio-military networks, where fixed and nom...
SAC
2011
ACM
12 years 8 months ago
2011
ACM
Regression testing is often performed with a time budget and it does not allow executing all test cases. Test case prioritization techniques re-order test cases to increase the ra...
ITC
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...