216 search results - page 2 / 44 » On High-Bandwidth Data Cache Design for Multi-Issue Processo... |
DATE
2003
IEEE
13 years 11 months ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
WMPI
2004
ACM
13 years 11 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
Recent I/O technologies such as PCI-Express and 10Gb Ethernet enable unprecedented levels of I/O bandwidths in mainstream platforms. However, in traditional architectures, memory ...
ARCS
2004
Springer
13 years 11 months ago
2004
Springer
Cryptographic methods are widely used within networking and digital rights management. Numerous algorithms exist, e.g. spanning VPNs or distributing sensitive data over a shared ne...
ISCAPDCS
2004
13 years 7 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...