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» On Programmable Memory Built-In Self Test Architectures
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DATE
2008
IEEE
112views Hardware» more  DATE 2008»
13 years 11 months ago
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in o...
Paolo Bernardi, Matteo Sonza Reorda
VEE
2012
ACM
232views Virtualization» more  VEE 2012»
12 years 24 days ago
DVM: towards a datacenter-scale virtual machine
As cloud-based computation becomes increasingly important, providing a general computational interface to support datacenterscale programming has become an imperative research age...
Zhiqiang Ma, Zhonghua Sheng, Lin Gu, Liufei Wen, G...
ICCD
2005
IEEE
246views Hardware» more  ICCD 2005»
14 years 2 months ago
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
Xizhen Xu, Sotirios G. Ziavras
FCCM
2002
IEEE
126views VLSI» more  FCCM 2002»
13 years 10 months ago
Hyperspectral Image Compression on Reconfigurable Platforms
NASA’s satellites currently do not make use of advanced image compression techniques during data transmission to earth because of limitations in the available platforms. With th...
Thomas W. Fry, Scott Hauck
DSN
2005
IEEE
13 years 11 months ago
Checking Array Bound Violation Using Segmentation Hardware
The ability to check memory references against their associated array/buffer bounds helps programmers to detect programming errors involving address overruns early on and thus avo...
Lap-Chung Lam, Tzi-cker Chiueh