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» On Test Scheduling for Core-Based SOCs
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ATS
2002
IEEE
136views Hardware» more  ATS 2002»
10 years 2 months ago
Recent Advances in Test Planning for Modular Testing of Core-Based SOCs
Test planning for core-based system-on-a-chip (SOC) designs is necessary to reduce testing time and test cost. In this paper, we survey recent advances in test planning that addre...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...
ASPDAC
2007
ACM
101views Hardware» more  ASPDAC 2007»
10 years 1 months ago
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
Abstract--An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed method...
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...
DSD
2009
IEEE
85views Hardware» more  DSD 2009»
10 years 4 months ago
Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment
—Long test application time and high temperature have become two major issues of system-on-chip (SoC) test. In order to minimize test application times and avoid overheating duri...
Zhiyuan He, Zebo Peng, Petru Eles
DATE
2008
IEEE
86views Hardware» more  DATE 2008»
10 years 4 months ago
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs
Abstract—Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testi...
Sudarshan Bahukudumbi, Krishnendu Chakrabarty, Ric...
VLSID
2002
IEEE
98views VLSI» more  VLSID 2002»
10 years 10 months ago
On Test Scheduling for Core-Based SOCs
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Sandeep Koranne
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