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VTS
2000
IEEE
94views Hardware» more  VTS 2000»
9 years 2 months ago
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...
Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng
DATE
2002
IEEE
114views Hardware» more  DATE 2002»
9 years 3 months ago
Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults
Test sets for path delay faults in circuits with large numbers of paths are typically generated for path delay faults associated with the longest circuit paths. We show that such ...
Irith Pomeranz, Sudhakar M. Reddy
ASPDAC
2004
ACM
112views Hardware» more  ASPDAC 2004»
9 years 3 months ago
Longest path selection for delay test under process variation
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, We...
ATS
2003
IEEE
131views Hardware» more  ATS 2003»
9 years 3 months ago
Software-Based Delay Fault Testing of Processor Cores
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hi...
ASPDAC
2006
ACM
155views Hardware» more  ASPDAC 2006»
9 years 4 months ago
Delay defect screening for a 2.16GHz SPARC64 microprocessor
This paper presents a case-study of delay defect screening applied to Fujitsu 2.16GHz SPARC64 microprocessor. A nonrobust delay test is used while each test vector is compacted to...
Noriyuki Ito, Akira Kanuma, Daisuke Maruyama, Hito...
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