187 search results - page 1 / 38 » On Using Efficient Test Sequences for BIST |
VTS
2002
IEEE
13 years 9 months ago
2002
IEEE
High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Inp...
IFIP
2001
Springer
13 years 9 months ago
2001
Springer
: High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single In...
DFT
2003
IEEE
13 years 9 months ago
2003
IEEE
A new hybrid BIST scheme is proposed which is based on using an “incrementally guided LFSR.” It very efficiently combines external deterministic data from the tester with on-c...
DSD
2005
IEEE
13 years 10 months ago
2005
IEEE
1 This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detecte...
ITC
1997
IEEE
13 years 8 months ago
1997
IEEE
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...