5 search results - page 1 / 1 » On optimal physical synthesis of sleep transistors |
ISPD
2004
ACM
13 years 9 months ago
2004
ACM
Considering the voltage drop constraint over a distributed model for power/ground (P/G) network, we study the following two problems for physical synthesis of sleep transistors: t...
JCP
2008
13 years 4 months ago
2008
Sleep transistors in industrial power-gating designs are custom designed with an optimal size. Consequently, sleep transistor P/G network optimization becomes a problem of finding ...
ISQED
2010
IEEE
13 years 11 months ago
2010
IEEE
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
DAC
2003
ACM
14 years 5 months ago
2003
ACM
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
INTEGRATION
2008
13 years 4 months ago
2008
Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the quality of the final design,...