42 search results - page 2 / 9 » On primitive fault test generation in non-scan sequential ci... |
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficien...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
DSD
2005
IEEE
13 years 11 months ago
2005
IEEE
Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subta...