315 search results - page 1 / 63 » On reducing load store latencies of cache accesses |
IPPS
2000
IEEE
13 years 8 months ago
2000
IEEE
Parallel programs that modify shared data in a cachecoherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisiti...
JSA
2010
13 years 2 months ago
2010
— Effective address calculation for load and store instructions needs to compete for ALU with other instructions and hence extra latencies might be incurred to data cache accesse...
EUROPAR
2010
Springer
13 years 5 months ago
2010
Springer
Abstract. Shared last level cache is crucial to performance. However, multithread program model incurs serious contention in shared cache. In this paper, to reduce average cache ac...
HPCA
2005
IEEE
14 years 4 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
EMSOFT
2009
Springer
13 years 11 months ago
2009
Springer
Scratchpads have been widely proposed as an alternative to caches for embedded systems. Advantages of scratchpads include reduced energy consumption in comparison to a cache and a...