315 search results - page 61 / 63 » On reducing load store latencies of cache accesses |
HIPC
2007
Springer
13 years 12 months ago
2007
Springer
: The Cell is a heterogeneous multi-core processor, which has eight co-processors, called SPEs. The SPEs can access a common shared main memory through DMA, and each SPE can direct...
ISCA
1996
IEEE
13 years 10 months ago
1996
IEEE
Historically, processor accesses to memory-mapped device registers have been marked uncachable to insure their visibility to the device. The ubiquity of snooping cache coherence, ...
MSS
2007
IEEE
14 years 1 days ago
2007
IEEE
Mariner is an iSCSI-based storage system that is de signed to provide comprehensive data protection on com modity ATA disk and Gigabit Ethernet technologies while offering the...
IJWMC
2007
13 years 5 months ago
2007
—Rapid advances in wireless networking have led to more mobile phones, PDAs, and other digital mobile devices becoming ubiquitously connected to the Internet. As the demand of de...
USENIX
1993
13 years 7 months ago
1993
Robotic storage devices offer huge storage capacity at a low cost per byte, but with large access times. Integrating these devices into the storage hierarchy presents a challenge ...