115 search results - page 3 / 23 » On the Design and Implementation of a Cache-Aware Multicore ... |
RTAS
2010
IEEE
13 years 3 months ago
2010
IEEE
Abstract—Recent results have shown that the feasibility problem of scheduling periodic tasks with self-suspensions is NPhard in the strong sense. We observe that a variation of t...
RTAS
2010
IEEE
13 years 3 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...
CBSE
2005
Springer
13 years 10 months ago
2005
Springer
We consider a class of component-based software models with interaction style of buffered asynchronous message passing between components with ports, represented by UML-RT. After ...
ADAEUROPE
2006
Springer
13 years 11 months ago
2006
Springer
When a middleware layer is designed for providing semi-transparent distribution facilities to real-time applications, a trade-off must be made between the expressiveness and contro...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
Dynamic voltage scaling (DVS) circuits have been widely adopted in many computing systems to provide tradeoff between performance and power consumption. The effective use of energ...