56 search results - page 10 / 12 » On the Performance of Fetch Engines Running DSS Workloads |
ISCA
2008
IEEE
14 years 5 days ago
2008
IEEE
Efficiently utilizing off-chip DRAM bandwidth is a critical issue in designing cost-effective, high-performance chip multiprocessors (CMPs). Conventional memory controllers deli...
ICSR
2004
Springer
13 years 11 months ago
2004
Springer
Quality assurance (QA) tasks, such as testing, profiling, and performance evaluation, have historically been done in-house on developer-generated workloads and regression suites. ...
SOSP
1997
ACM
13 years 7 months ago
1997
ACM
Despite a large research effort, software distributed shared memory systems have not been widely used to run parallel applications across clusters of computers. The higher perform...
IPPS
2007
IEEE
14 years 2 days ago
2007
IEEE
1 Multi-paradigm, multi-threaded and multi-core computing devices available today provide several orders of magnitude performance improvement over mainstream microprocessors. These...
PPSC
2001
13 years 7 months ago
2001
Crew pairing generation is a time consuming part of the complex process of airline crew scheduling. We present a parallel algorithm for this problem's solution and several im...