3 search results - page 1 / 1 » On the Realisation of Delay-Insensitive Asynchronous Circuit... |
ASYNC
1997
IEEE
13 years 8 months ago
1997
IEEE
The realisation of Delay-Insensitive (DI) asynchronous circuits with a CMOS ternary logic is described in this paper. The main advantage of temary logic is the easy realisation of...
ISMVL
1997
IEEE
13 years 8 months ago
1997
IEEE
This paper shows how the application of a CMOS ternary logic is useful in the realisation of Delay Insensitive (01)asynchronous circuits. It is shown that fully DIasynchronous cir...
ISQED
2009
IEEE
13 years 11 months ago
2009
IEEE
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...