56 search results - page 3 / 12 » On the speedup required for combined input- and output-queue... |
GLOBECOM
2006
IEEE
14 years 6 days ago
2006
IEEE
— Combined input-crosspoint buffered (CICB) packet switches with dedicated crosspoint buffers require a minimum amount of memory in the buffered crossbar of N2 × k × L, where N...
INFOCOM
2000
IEEE
13 years 10 months ago
2000
IEEE
— We consider cell-based switch architectures, whose internal switching matrix does not provide enough speed to avoid input buffering. These architectures require a scheduling al...
TON
2002
13 years 5 months ago
2002
Abstract--We propose an efficient parallel switching architecture that requires no speedup and guarantees bounded delay. Our architecture consists of input
HOTI
2002
IEEE
13 years 11 months ago
2002
IEEE
We present the architecture and practical VLSI implementation of a 4-Tb/s single-stage switch. It is based on a combined input- and crosspoint-queued structure with virtual output...
INFOCOM
2000
IEEE
13 years 10 months ago
2000
IEEE
— In this paper we use fluid model techniques to establish two results concerning the throughput of data switches. For an input-queued switch (with no speedup) we show that a ma...