111 search results - page 2 / 23 » On the value locality of store instructions |
ICS
1999
Tsinghua U.
13 years 9 months ago
1999
Tsinghua U.
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
ASPLOS
2006
ACM
13 years 9 months ago
2006
ACM
Transient faults are expected a be a major design consideration in future microprocessors. Recent proposals for transient fault detection in processor cores have revolved around t...
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
The physical register file is an important component of a dynamically-scheduled processor. Increasing the amount of parallelism places increasing demands on the physical register...
ICPP
1999
IEEE
13 years 9 months ago
1999
IEEE
On-line transaction processing exhibits poor memory behavior in high-end multiprocessor servers because of complex sharing patterns and substantial interaction between the databas...