66 search results - page 1 / 14 » On-Chip Inductance in X Architecture Enabled Design |
ISQED
2007
IEEE
13 years 10 months ago
2007
IEEE
The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition tim...
DAC
2001
ACM
14 years 5 months ago
2001
ACM
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
DAC
1999
ACM
13 years 8 months ago
1999
ACM
As the family of Alpha microprocessors continues to scale into more advanced technologies with very high frequency edge rates and multiple layers of interconnect, the issue of cha...
DAC
1998
ACM
14 years 5 months ago
1998
ACM
Because magnetic e ects have a much longer spatial range than electrostatic e ects, an interconnect line with large inductance will be sensitive to distant variations in interconn...
DAC
1998
ACM
14 years 5 months ago
1998
ACM
- A closed form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicromete...