10 search results - page 1 / 2 » On-chip communication and synchronization mechanisms with ca... |
CF
2010
ACM
13 years 10 months ago
2010
ACM
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
CLUSTER
2009
IEEE
13 years 2 months ago
2009
IEEE
Scientific computing has seen an immense growth in recent years. The Message Passing Interface (MPI) has become the de-facto standard for parallel programming model for distribute...
COMPCON
1995
IEEE
13 years 8 months ago
1995
IEEE
This paper describes Tempest, a collection of mechanisms for communication and synchronization in parallel programs. With these mechanisms, authors of compilers, libraries, and ap...
EUROPAR
2001
Springer
13 years 9 months ago
2001
Springer
As the technology for high-speed networks has evolved over the last decade, the interconnection of commodity computers (e.g., PCs and workstations) at gigabit rates has become a re...
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...