In current networks, packet losses can occur if routers do not provide sufficiently large buffers. This paper studies how many buffers should be provided in a router to eliminat...
In this paper we extend the study of flow-energy scheduling to a model that allows both sleep management and speed scaling. Our main result is a sleep management algorithm called I...
Tak Wah Lam, Lap-Kei Lee, Hing-Fung Ting, Isaac Ka...
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
The past few years have witnessed a number of interesting online algorithms for deadline scheduling in the dynamic speed scaling model (in which a processor can vary its speed to ...
Traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the ...