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EMSOFT
2004
Springer
13 years 10 months ago
An approach for integrating basic retiming and software pipelining
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...
Noureddine Chabini, Wayne Wolf
EUC
2005
Springer
13 years 10 months ago
Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs
Abstract. Loop distribution and loop fusion are two effective loop transformation techniques to optimize the execution of the programs in DSP applications. In this paper, we propo...
Meilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, M...
LCTRTS
1999
Springer
13 years 9 months ago
Effective Exploitation of a Zero Overhead Loop Buffer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanj...
CODES
2003
IEEE
13 years 10 months ago
Design space minimization with timing and code size optimization for embedded DSP
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-M...
CODES
2005
IEEE
13 years 10 months ago
Iterational retiming: maximize iteration-level parallelism for nested loops
Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP) applications. It is important to study effective and efficient transformation ...
Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean ...