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ICCAD
2001
IEEE
184views Hardware» more  ICCAD 2001»
14 years 2 months ago
CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
Cagdas Akturan, Margarida F. Jacome
CODES
2005
IEEE
13 years 11 months ago
Iterational retiming: maximize iteration-level parallelism for nested loops
Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP) applications. It is important to study effective and efficient transformation ...
Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean ...
CC
2006
Springer
129views System Software» more  CC 2006»
13 years 9 months ago
Loop Transformations in the Ahead-of-Time Optimization of Java Bytecode
Abstract. Loop optimizations such as loop unrolling, unfolding and invariant code motion have long been used in a wide variety of compilers to improve the running time of applicati...
Simon Hammond, David Lacey
CODES
2003
IEEE
13 years 11 months ago
Design space minimization with timing and code size optimization for embedded DSP
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-M...
EUC
2005
Springer
13 years 11 months ago
Optimizing Nested Loops with Iterational and Instructional Retiming
Abstract. Embedded systems have strict timing and code size requirements. Retiming is one of the most important optimization techniques to improve the execution time of loops by in...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...