15 search results - page 3 / 3 » Optimal Code Size Reduction for Software-Pipelined and Unfol... |
LCTRTS
1999
Springer
13 years 9 months ago
1999
Springer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
TC
1998
13 years 5 months ago
1998
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Software implementations of modern block ciphers often require large lookup tables along with code size increasing optimizations like loop unrolling to reach peak performance on g...
PLDI
1990
ACM
13 years 9 months ago
1990
ACM
- This paper describes techniques for optimizing range checks performed to detect array bound violations. In addition to the elimination of range check:s, the optimizations discuss...
CF
2009
ACM
13 years 12 months ago
2009
ACM
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...