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» Optimal cell flipping in placement and floorplanning
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DAC
2006
ACM
14 years 4 months ago
Optimal cell flipping in placement and floorplanning
In a placed circuit, there are a lot of movable cells that can be flipped to further reduce the total wirelength, without affecting the original placement solution. We aim at solv...
Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N...
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
14 years 17 days ago
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzh...
FPGA
1998
ACM
125views FPGA» more  FPGA 1998»
13 years 7 months ago
Timing Driven Floorplanning on Programmable Hierarchical Targets
The goal of this paper is to perform a timing optimization of a circuit described by a network of cells on a target structure whose connection delays have discrete values following...
S. A. Senouci, A. Amoura, Helena Krupnova, Gabriel...
TVLSI
2010
12 years 10 months ago
Pattern Sensitive Placement Perturbation for Manufacturability
The gap between VLSI technology and fabrication technology leads to strong refractive effects in lithography. Consequently, it is a huge challenge to reliably print layout features...
Shiyan Hu, Patrik Shah, Jiang Hu
ICCAD
2009
IEEE
109views Hardware» more  ICCAD 2009»
13 years 1 months ago
CRISP: Congestion reduction by iterated spreading during placement
Dramatic progress has been made in algorithms for placement and routing over the last 5 years, with improvements in both speed and quality. Combining placement and routing into a ...
Jarrod A. Roy, Natarajan Viswanathan, Gi-Joon Nam,...