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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 6 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
IEEEPACT
2009
IEEE
14 years 21 days ago
Interprocedural Load Elimination for Dynamic Optimization of Parallel Programs
Abstract—Load elimination is a classical compiler transformation that is increasing in importance for multi-core and many-core architectures. The effect of the transformation is ...
Rajkishore Barik, Vivek Sarkar
LCTRTS
2005
Springer
13 years 11 months ago
Cache aware optimization of stream programs
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...
Janis Sermulins, William Thies, Rodric M. Rabbah, ...
LCTRTS
2009
Springer
14 years 25 days ago
Eliminating the call stack to save RAM
Most programming languages support a call stack in the programming model and also in the runtime system. We show that for applications targeting low-power embedded microcontroller...
Xuejun Yang, Nathan Cooprider, John Regehr
COR
2002
95views more  COR 2002»
13 years 5 months ago
Dynamic lot sizing and tool management in automated manufacturing systems
The overall aim of this study is to show that there is a critical interface between the lot sizing and tool management decisions, and these two problems cannot be viewed in isolat...
M. Selim Akturk, Siraceddin Onen