54 search results - page 1 / 11 » Optimal simultaneous mapping and clustering for FPGA delay o... |
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
DAC
2000
ACM
14 years 5 months ago
2000
ACM
FPGA routing resources typically consist of segments of various lengths. Due to the segmented routing architectures, the traditional measure of wiring cost (wirelength, delay, con...
DAC
2001
ACM
14 years 5 months ago
2001
ACM
In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven m...
ISLPED
2004
ACM
13 years 9 months ago
2004
ACM
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
DATE
2000
IEEE
13 years 8 months ago
2000
IEEE
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...