11 search results - page 2 / 3 » Optimal wire and transistor sizing for circuits with non-tre... |
ARITH
2007
IEEE
13 years 9 months ago
2007
IEEE
In this paper we explore the relationship between adder topology and energy efficiency. We compare the energy-delay tradeoff curves of selected 32-bit adder topologies, to determi...
ISPD
2004
ACM
13 years 10 months ago
2004
ACM
This paper presents an efficient method for optimizing the design of power/ground (P/G) networks by using locally regular, globally irregular grids. The procedure divides the pow...
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
The circuit tuning problem is best approached by means of gradient-based nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the o...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
One of the main tasks in analog design is the sizing of the circuit parameters, such as transistor lengths and widths, in order to obtain optimal circuit performances, such as hig...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...