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DAC
2006
ACM
11 years 20 days ago
Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming
In this paper, we propose an exact algorithm for the problem of area optimization under a delay constraint in the synthesis of multiplierless FIR filters. To the best of our knowl...
Eduardo A. C. da Costa, José Monteiro, Leve...
DATE
2006
IEEE
124views Hardware» more  DATE 2006»
10 years 5 months ago
Timing-driven cell layout de-compaction for yield optimization by critical area minimization
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
ICESS
2007
Springer
10 years 5 months ago
A Design Method for Heterogeneous Adders
The performance of existing adders varies widely in their speed and area requirements, which in turn sometimes makes designers pay a high cost in area especially when the delay req...
Jeong-Gun Lee, Jeong-A. Lee, Byeong-Seok Lee, Milo...
PATMOS
2007
Springer
10 years 5 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...
TCAD
2008
172views more  TCAD 2008»
9 years 11 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
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